Research

CGRA Architecture & Compilation

Coarse-Grained Reconfigurable Arrays (CGRAs) offer a promising balance between the flexibility of processors and the efficiency of ASICs. Our lab has developed a comprehensive ecosystem for CGRA design and compilation:

  • Architecture Modeling — HETA, HierCGRA, and FDRA provide flexible frameworks for modeling heterogeneous, hierarchical, and dynamically reconfigurable CGRA architectures.
  • Mapping & Compilation — GRAFT uses GNN-based adaptive mapping; TransMap leverages Transformer and deep reinforcement learning; the Adora compiler provides end-to-end optimization for dataflow acceleration and task pipelining.
  • Design Space Exploration — AUGER, MoDAF, and LEMOE employ multi-objective Bayesian optimization and LLM-enhanced techniques for efficient architecture exploration.
  • Application Frameworks — COFFA enables fused-grained architecture design for irregular loops; CFEACT targets agile CNN and Transformer acceleration; CGRA-HD supports hyperdimensional computing.

FPGA Architecture Innovation

We explore novel FPGA architectural components to improve area, performance, and power efficiency:

  • LUT Architectures — RLUT provides reduced LUT architectures with fine-grained scalability; DSLUT introduces asymmetric LUT designs with automated design flows based on practical function analysis.
  • Routing Architectures — VIB (Versatile Interconnection Block) offers a flexible routing architecture with bent wires for improved routability.
  • PLB Exploration — Investigating programmable logic block designs combining LUTs and microgates.
  • Transistor Sizing — Two-phase optimization using Bayesian methods for FPGA transistor sizing.

EDA Algorithms & Optimization

Our group advances fundamental EDA algorithms for reconfigurable computing:

  • Logic Synthesis — NPN classification, Boolean matching, and technology mapping algorithms.
  • Timing Optimization — Iterative and verifiable retiming for performance optimization; yield-driven clock skew scheduling using generalized extreme value distributions.
  • Design Space Exploration — Multi-objective DSE for HLS via Bayesian optimization (Best Paper Award at ISEDA 2023).
  • Approximate Computing — Efficient approximate multiplier generation for FPGAs.

AI Acceleration on Reconfigurable Hardware

We develop efficient accelerator designs for AI workloads on reconfigurable platforms:

  • CNN & Transformer Acceleration — CFEACT provides a unified framework for agile CNN and Transformer accelerator design on CGRAs.
  • Data Parallelism — Techniques for efficient data parallelism on spatial CGRAs via constraint satisfaction and graph coloring.
  • Vector-Dataflow Execution — DynVec provides an end-to-end framework combining vector processing with dataflow execution for flexible acceleration.
  • Emerging Paradigms — CGRA-HD explores hyperdimensional computing on reconfigurable accelerators.

Open-Source Contributions

We believe in open-source collaboration to advance reconfigurable computing research. Our frameworks and tools are available to the community, enabling reproducible research and fostering innovation in hardware-software co-design.