Professor, PI
Fudan University
FPGA architecture, CGRA design, EDA algorithms, reconfigurable computing
CGRA architecture (HETA, COFFA), data parallelism
DSE frameworks (AUGER, MoDAF, TransMap, LEMOE)
Retiming, clock skew scheduling
Transistor sizing, DynVec
Workload deployment, Adora compiler
HierCGRA
FDRA framework, CGRA front-end
CGRA mapping (GRAFT), MLIR compiler
CFEACT framework, CNN/Transformer acceleration
RLUT, DSLUT architectures
CGRA front-end compiler
HLS DSE, Bayesian optimization
